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| IN74HC161A PRESETTABLE COUNTERS High-Performance Silicon-Gate CMOS The IN74HC161A is identical in pinout to the LS/ALS161. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC161A is programmable 4-bit synchronous counter that feature parallel Load, asynchronous Reset, a Carry Output for cascading and count-enable controls. The IN74HC161A is binary counter with asynchronous Reset. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices * * * * ORDERING INFORMATION IN74HC161AN Plastic IN74HC161AD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Rese t L H H H H H Load X L H H H X Inputs Enable Enable P T X X X X X L L X H H X X Clock X Q0 L P0 Outputs Q1 Q2 L L P1 P2 No change No change Count up No change Q3 L P3 Function Reset to "0" Preset Data No count No count Count No count X=don't care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3 1 IN74HC161A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Current, per Pin mA 25 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HC161A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V 85 125 25 C to C C -55C 1.5 1.5 VOUT=0.1 V or VCC-0.1 V 2.0 1.5 VIH Minimum High3.15 3.15 3.15 Level Input 4.5 IOUT 20 A 4.2 4.2 4.2 Voltage 6.0 0.5 0.5 VOUT=0.1 V or VCC-0.1 V 2.0 0.5 VIL Maximum Low 1.35 1.35 1.35 Level Input 4.5 IOUT 20 A 1.8 1.8 1.8 Voltage 6.0 1.9 1.9 VIN=VIH or VIL 1.9 VOH Minimum High2.0 4.4 4.4 4.4 Level Output 4.5 IOUT 20 A 5.9 5.9 5.9 Voltage 6.0 VIN=VIH or VIL 3.7 3.84 3.98 4.5 IOUT 6.0 mA 5.2 5.34 5.48 6.0 IOUT 7.8 mA 0.1 0.1 VIN=VIH or VIL 0.1 VOL Maximum Low2.0 0.1 0.1 0.1 Level Output 4.5 IOUT 20 A 0.1 0.1 0.1 Voltage 6.0 VIN=VIH or VIL 0.4 0.33 0.26 4.5 IOUT 6.0 mA 0.4 0.33 0.26 6.0 IOUT 7.8 mA IIN Maximum Input VIN=VCC or GND 6.0 0.1 1.0 1.0 Leakage Current VIN=VCC or GND ICC Maximum 6.0 4.0 40 160 Quiescent Supply IOUT=0A Current (per Package) Unit V V V V A A 3 IN74HC161A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 C 85C 125 to C -55C 4 5 6 fmax Maximum Clock Frequency (Figures 1,6) 2.0 20 24 30 4.5 24 28 35 6.0 200 160 120 2.0 tPLH 28 23 20 4.5 22 20 16 6.0 Maximum Propagation Delay Clock to Q 320 185 145 tPHL (Figures 1,6) 2.0 30 25 22 4.5 23 20 18 6.0 220 185 145 tPHL Maximum Propagation Delay Reset to Q 2.0 25 22 20 (Figures 2 and 6) 4.5 21 19 17 6.0 190 150 110 2.0 tPLH 20 18 16 4.5 17 15 14 Maximum Propagation Delay Enable T to 6.0 Ripple Carry Out 210 175 135 tPHL (Figures 3,6) 2.0 22 20 18 4.5 20 16 15 6.0 200 160 120 2.0 tPLH 30 27 22 4.5 25 22 18 Maximum Propagation Delay Clock to 6.0 Ripple 220 185 145 tPHL Carry Out (Figures 1,6) 2.0 35 28 22 4.5 28 24 20 6.0 230 190 155 tPHL Maximum Propagation Delay Reset to 2.0 30 26 22 Ripple Carry Out (Figures 2,6) 4.5 25 22 18 6.0 110 95 75 tTLH, tTHL Maximum Output Transition Time, Any 2.0 22 19 15 4.5 Output 19 16 13 6.0 (Figures 1 and 6) CIN Maximum Input Capacitance 10 10 10 Power Dissipation Capacitance (Per Gate) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25C,VCC=5.0 V 30 pF Unit MHz ns ns ns ns ns ns ns ns ns pF CPD 4 IN74HC161A TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) Symbol Parameter VCC V Guaranteed Limit 25 C 85C 125 C to -55C 80 60 40 30 20 15 20 18 12 90 75 60 30 20 15 20 18 12 110 95 80 35 25 20 25 23 17 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 110 95 80 26 20 15 23 17 12 110 95 80 26 20 15 23 17 12 90 75 60 18 15 12 15 13 10 90 75 60 18 15 12 15 13 10 1000 1000 1000 500 500 500 400 400 400 Unit tSU tSU tSU th th trec trec tw tw tr, tf Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) Minimum Setup Time, Load to Clock (Figure 4) Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) Minimum Hold Time, Clock to Load or Preset Data Inputs (Figure 4) Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Recovery Time, Load Inactive to Clock (Figure 4) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 ns ns ns ns ns ns ns ns ns ns 5 IN74HC161A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit 6 IN74HC161A VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. Figure 7.Expanded logic diagram 7 IN74HC161A 1. 2. 3. 4. Sequence illustrated in waveforms: Reset outputs to zero. Preset to binary twelve. Count to thirteen, fourteen, fifteen, zero, one, and two. Inhibit. Figure 8. Timing Diagram 8 IN74HC161A TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter 9 |
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